1. Field of the Invention
The present invention relates to a novel method and system for optimizing integrated circuit layouts in order to maximize a dynamically defined lithographic process in which lithographic tolerances are not applied at fixed edge locations, in order to achieve a larger process window for printing a functional circuit than is attainable with conventional design rules.
Lithographic constraints are important factors in determining the efficiency of a circuit layout. In essence, lithographic constraints are conventionally determined by the generally limited capability of a lithographic process to successfully print edges at specified positions within tolerances. A lithographic process involves using a lithographic exposure tool to illuminate a lithographic mask from a range of directions, and focusing a projected image of the mask onto a photosensitive film that coats a partially fabricated integrated circuit on a wafer, such as a silicon wafer. Lithographic process window represents the range of delivered light energy (dose) and image plane defocus within which the projected image adequately represents the desired circuit shapes. After the image is formed, the photosensitive film is developed, and the printed pattern is transferred into a functional process layer in the circuit. The final circuit then consists of many such patterned levels stacked atop one another.
2. Discussion of the Prior Art
FIG. 1 shows the general system flow of the most commonly used prior art Optical Proximity Correction (OPC) process, which is termed shape-directed OPC. In shape-directed OPC, certain aspects of the lithographic process (usually the positions of feature edges on the mask) are iteratively adjusted to make the printed shapes conform to the design shapes. (Design shapes are the often rectangular shapes provided by the circuit designers.) Thus, in conventional shape-directed OPC the edges are placed exactly at the specified positions, i.e. in shape-directed OPC no error margin is allowed in the focused image.
FIG. 2 shows a prior art form of OPC that is more intensive computationally than shape-directed OPC; the FIG. 2 form is referred to here as conventional process-window OPC. In conventional process-window OPC the lithographic process is adjusted in order to maximize the range of dose and focus within which the printed edge positions fall within a tolerance band surrounding the nominal positions. Tolerance band refers to a range of acceptable positions about the nominal design position.
The FIG. 2 process remains predominantly a post-design process with the intent of making the projected shapes adequately resemble the design shapes.
Acceptable tolerances for the printed shapes must yield successful circuit performance, and must also be readily maintained under typical process variations. However, lithographic capability for printing a given feature edge is dependent on other features in the same local region of the circuit layout, as is circuit functionality. Consequently, lithographic constraints should ideally be very dynamic, and potentially incorporate and take advantage of the particular configurational details of large numbers of different local circuit cases. Generally, however, due to general and practical design reasons, lithographic constraints are usually provided a highly simplified form, known in the technology as design rules, with these rules determining a lithographic capability, in effect, an achievable lithographic process window, which is at least acceptable in the technology, and these rules are normally employed for the entire circuit layout.
A lithographic process window is ordinarily defined in the technology as the exposure/focus range within which all printed edges of a specific design are successfully placed at predetermined positions, specifically within given tolerances. In essence, these given tolerances represent a reasonable vehicle for predicting the defocus and dose sensitivity of a fully fixed circuit design, such as a fixed set of target patterns. When utilized for process-window OPC, such tolerances facilitate optimization of the lithographic mask in a manner whereby image edges will print at the desired positions with the least possible sensitivity to encountered dose and focus fluctuations. This signifies that, in effect, the lithographic process is optimally configured in order to print the fixed circuit pattern.
However, it would be preferable to take lithographic feasibility into account prior to fixing the target positions; in effect, to take into consideration lithographic feasibility, as well as circuit performance, in deciding upon the positions and tolerances of the printed feature edges. In this connection, circuit requirements are used in the present invention predominantly only to fix mutual constraints on feature edges, and not to impart rigid constraints on absolute edge position.
Ideally, the projected shapes should be electrically optimized in order to maximize circuit performance requirements, and thereafter, lithographically optimized in order to obtain electrically desirable shapes and with these steps then having been iterated as necessary to be able to achieve the best overall solution in process optimization. Unfortunately, it is computationally very difficult to reassess electrical performance after every iteration. The conventional ground rule procedure of reducing electrical requirements to fixed bands of allowed edge positions has the advantage that process window calculation is relatively easy, in that intensity need only be calculated (in each focal plane) at the fixed positions occupied by edges that fall at the upper and lower tolerance limits. Conventional shape-directed OPC nominally involves a single intensity calculation for each edge (fragmentation point), but present methods for taking resist and process bias into account actually require several intensity calculations per fragmentation point.
In mathematical terms, the constraints in shape-directed OPC take the formxj=pj,  [1]i.e. they simply specify that the jth edge be placed at position pj. As it is conventionally conceived, process-window OPC seeks to maximize process window in the face of constraints which take the form:xj−pj≦dj,pj−xj≦dj,  [2a]i.e. the masks or other process parameters are adjusted in order to maximize the range of dose and focus over which the jth edge is printed within a tolerance ±dj of nominal position pj. Even conventional constraints can be asymmetrical between inner and outer tolerances, i.e. instead of eq. [2a] they can take the formxj−pj≦ej,pj−xj≦sj.  [2b]
Constraints of the eq.2a or b form are often imposed on each edge of what can be considered a pair of edges, since simple circuit shapes have two edges across each dimension, for example, left and right edges. If, for example, the jth edge is the right edge of a particular circuit feature, and the ith edge is this feature's left edge, then in many cases it is the width of the feature, xj−xi, that is electrically critical. Such electrically critical widths are customarily referred to as critical dimensions, or CDs. In this example, eq.2b would be supplemented by a similar constraint for the ith (left) edge:xi−pi≦si,pi−xi≦ei.  [2c]The tolerance on contraction of the CD, that is to say the tolerance on shrinkage of xj−xi, would be 2sj in this example, and the tolerance on expansion 2ej. Similar tolerances are often applied to the spaces between features. This is illustrated in FIG. 5.
Conventional constraints in the form of eq.2a-c have the advantage that the boundaries of the lithographic process window within which the constraints are satisfied can be established by determining the intensity, in different focal planes, at two transverse positions, for example the positions pj+ej and pj−sj in the case of eq.2b. However, these conventional constraints have the drawback that they excessively constrain the individual feature edges from an electrical point of view, for example converting two electrically necessary constraints xj−xi>pj−pi−2sj and xj−xi>pj−pi+2ej into the four constraints listed in eqs.2a and 2b. This occurs because electrically relevant constraints on feature width or spacing are converted into pairs of constraints involving adjacent edges of the feature. Though the total number of constraints may not be increased by this procedure, the constraints applied to a particular edge are stronger than necessary.
Many approaches have been developed to optimally place circuit features from an electrical point of view.
Chiluvuri, et al., U.S. Pat. No. 6,434,721 B1, discloses a method and apparatus for a constraint graph based layout technique, which facilitates a compact arrangement of circuits in two dimensions. In that instance, the layout is converted to a constraint graph representation and weight values are assigned to respective shear and jogging edges, thereby providing an optional cutset.
Lin, et al., U.S. Pat. No. 5,892,261, provides for a method of layout design edge spacing of VDD contacts to be increased so that internal circuit electrostatic discharge (ESD) immunity is increased without impacting device dimension and layout area constraints.
Suda, U.S. Pat. No. 5,889,681, relates to a method of arranging abstract cells in target cells, and setting compaction constraints to the edge of abstract cell in the layout of semiconductor integrated circuits.
Drumm, U.S. Pat. No. 5,825,661 provides a post layout optimization of integrated circuits in which circuit locations are assigned for allowable physical locations for new circuit elements.
Patel, U.S. Pat. No. 5,764,532; Hao, et al., U.S. Pat. No. 5,612,893; Bamji, U.S. Pat. Nos. 5,581,474 and 5,568,396; Edwards, U.S. Pat. Nos. 5,416,722 and 5,515,293; and Ishii, et al., U.S. Pat. No. 4,805,113, each respectively disclose or describe various methods of updating layouts of circuit elements in order to optimize integrated circuit designs. None of these methods of the prior art publications, while employing constraints including etch definitions on an integrated circuit layout, provide for the simultaneous optimizing of the layout of electrical circuits and lithographic masks, which would be analogous to the lithographic process window optimization as uniquely contemplated by the present invention.
Similarly, the IBM Technical Disclosure Bulletin Volume 35 No. 4B of September 1992, and Vol. 30, No. 7 of December 1987, describe various optimizations in order to improve upon integrated circuit layouts; and similar layout optimization for electronic design arrangements is described in International Patent Publication No. WO 01/65424 A2.